Hardware Engineer Resume - Sample
Faizal
E-Mail : faXXXX.vlsi@XXXXX.com
Phone No: +9198XXXXXX
Experience Summary
- I am working as a Senior Engineer Consultant in XXXXXXX Communication Technologies, having total experience of 5.4 years which includes 7 months project training.
- I have specialized on SOC Validation and Verification, SOC Gate level simulation, FPGA Design and Verification.
- I have worked on x86, V53A Processor IP, AHB, SD/SDIO/SDXC host Controller IP, SDIO-UART Bridge IP development, SPI master in my career.
Career Goals
- To seek a challenging and career oriented job, which enables me to update with the emerging latest Technology and provides scope for widening the spectrum of my knowledge.
- My career aspirations revolve around job satisfaction, responsibilities and to an extent on the remuneration offered to me.
- Ambitious, positive attitude, hard working and fast on-the-job learning are my strengths.
- With my technical and communication skills, I am confident of handling any suitable assignment in projects and rise to the occasion and time.
Professional Qualification
- Master of Engineering in VLSI Systems (Year 2005 - 2007) From XXXXXXX College.
Academic Profile
- M.Tech-VLSI Systems, National Institute of Technology, Percentage : 7.9 CGPA = 79%
- BE. - Electronics and Communication Engineering, Percentage : 85.12%
- XII-std, Percentage : 89.08%
- X-std, Percentage : 85.4%
Skills Set
Operating system: WINDOWS, Linux, Solaris
HDLs: Verilog
HVL: Open Vera
Simulators: Modelsim, Novas Verdi
FPGA Tools: Xilinx ISE and Actel Libero
FPGAs: Xilinx Spartan3E, Spartan3AN, Spartan6 and Actel ProASIC3
Processors: Intel x86 ,NEC V53A and ARM7
Programming Languages: Assembly, C, C++, Shell scripting and TCL
Bus Architectures: SDXC, SDIO, Wishbone, AHB, UART, SPI
Memory Interfaces: DDR2 SDRAM
Hardware tools: Tektronix Logic Analyzer and DSO
Emulation tools: Quickturn palladium
Job Experience
Company: XXXXXXXX Communication Technologies Pvt. Ltd.
Role: Senior Hardware Design Engineer
Domain: SOC (GLS-PTE)
Programming Languages: OpenVera, Shell Scripting
Operating Systems: Solaris
Project Details
Project 1: MSM8x30 chipset(current project)
Description:- The xxxxxxxx MSM8x30 chipset is the first chip to include MIPI combo PHY with 28nm technology.
- It has lower power consumption.It features Dual krait processor and used for smartphone applications.
Duration: 9 months.
Team size: 4 members.
Contribution: Gate level simulation and VT simulation of SDCC4 and GSBI blocks.
Domain: SOC.
Technology Skills: System Verilog, Shell scripting.
Project 2: Subarctic chip
Description:- Subarctic is a low cost Cortex-A8 based application processor targeted at existing ARM9/ARM11 base of customers that need more processing capabilities.
- Subartctic integrate sabertooth and various other peripheral and interfaces.It is designed in 45nm.
- Targeted for Home automation/networking, Gaming peripherals, Consumer medical appliance, Printers, Building automation, Smart Toll systems, Vending machines, Weighing Scale, Educational consoles, Toys, HMI, Satellite radio, Customer Premise Equipment (CPE), Portable Navigation Devices (PND), IP Phone (IPP).
Duration: 18 months.
Team size:6 members.
Contribution: Emulation( Pre-Silicon, Post-Silicon Validation) and Test case debug.
Domain: SOC.
Technology Skills: Shell scripting.
Project 3: Verification of V53A FPGA Processor
Description:- The design implements uPD70236A CPU core targeted into a single Xilinx Spartan-6 series.
- All the integrated peripherals are tested using the automated test environment.
Duration: 11 months.
Team size: 3 members.
Contribution: Test plan, Test case, Simulation and Target testing.
Domain: FPGA Verification.
Technology Skills: Verilog.
Project 4: SDXC Host Controller IP Verification
Description:- Supports 32 bit AHB LITE synchronous Slave interface working at interface frequency.
- 1 -bit/4-bit modes of SD/SDIO supported.
- Supports various clock frequencies such as 25MHz, 50MHz, 100MHz required for SD/ SDIO operations.
- Operating frequency configurable through registers.
- It is Compliant with SD specification version 3.0.
Duration : 16 months.
Team size: 2 members.
Contribution: Test plan, Test Case, Simulation and Target testing.
Domain: FPGA Verification.
Technology Skills: Verilog.
Project 5: Digital Image browser (iChart) Application
Description:- The SPI controller primary function is to read configuration settings from the data flash after power on and also write the configuration settings into it.
- It consists of SPI master state machine and shifter logic.
- Read/write operation to and from the data flash can be accomplished by sending commands, address and data using the SPI controller.
Duration: 8 months.
Team size: 4 members.
Contribution: SPI Controller and Application Control logic RTL design, Test plan, Test Case, Simulation and testing.
Domain: FPGA Design and Verification.
Technology Skills: Verilog.
Awards / Prizes
- Received “Project Quality Appreciation Award” while working in iWave Systems Technologies Pvt Ltd.
- College Second in Graduation.
- Third prize in paper presentation (National level) in Kumaraguru College of Technology, Coimbatore.
- Won First place in Weight-lifting(University Level).
Extra-curricular Activities and Hobbies
- Listening to Music & GYM.
- Playing football.
Personal Profile
Date of Birth:Present Address:Passport No:
