What is Netlist in logic synthesis?

Q.  In logic synthesis, ________ is an EDIF that gives the description of logic cells & their interconnections.
- Published on 25 Nov 15

a. Netlist
b. Checklist
c. Shitlist
d. Dualist

ANSWER: Netlist
 

    Discussion

  • hansraj   -Posted on 19 Dec 16
    if i process this information on the net

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