1) Which clock pulses are generated by the microprocessor so as to handle the timing and control operations related to internal functioning level?
a. Single phase clock pulses
b. Multi-phase clock pulses
c. Anti-phase clock pulses
d. None of the above
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2) The bus-request control input of micro-processor indicates the temporary suspension of current operation by driving all buses into________.
a. high impedance state
b. low impedance state
c. Both a & b
d. None of the above
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3) Which feature conducts the memory transfer by controlling the address and data buses on the basis of request originated by the device when buses get disabled by the microprocessor?
a. Indirect Memory Access
b. Direct Memory Access
c. Read Memory Access
d. Write Memory Access
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4) Where is the operation code of an instruction get transferred for the determination of sequences required in executing the operations?
a. Instruction Register
b. Status Register
c. Accumulator Register
d. Temporary Register
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5) Which source/s play a significant role in delivering the information to the address buffers?
a. Stack Pointer
b. Address Register
c. Program Counter
d. All of the above
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6) Which parameter/s is/ are of relevant importance regarding the time interval of memory cycle specified by the microprocessor?
a. Internal clock frequency and access time
b. External clock frequency and access time
c. Internal as well as external clock frequencies
d. Only access time
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7) Which form of special control unit enables the memory to adjust or set its own timing of memory cycle in the microprocessors?
a. Set
b. Reset
c. Ready
d. Enable
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8) Which among the below stated operating condition implies that the contents of register C get deliver to a memory byte at the definite address specified by AR?
a. M [AR] → C
b. M [AR] ← C
c. AR → M [C]
d. AR ← M [C]
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9) Which add instruction/s occupy the three memory bytes in accordance to the various length format acquired at the stage of microprocessor sequencing?
a. Add B to A
b. Add immediate operand to A
c. Add operand specified by an address to A
d. All of the above
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10) Which data-bus has a proficiency of reducing the number of accesses to memory in response to the speed related shortcomings displayed by 8-bit microprocessor?
a. 8 - bit data bus
b. 16 - bit data bus
c. 24 - bit data bus
d. 32 - bit data bus
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11) How many memory cycles should the microprocessor undergo for an execution of instructions, especially the instruction include the address of the operand?
a. 2 memory cycles
b. 4 memory cycles
c. 8 memory cycles
d. Any number depending upon the number of operands in the instruction
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12) Which category of microprocessor instructions detect the status conditions in registers and accordingly exhibit the variations in program sequence on the basis of detected results?
a. Transfer Instructions
b. Operation Instructions
c. Control Instructions
d. All of the above
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13) The push and pop instructions belonging to the category of transfer instructions of microprocessor perform data transformation between _______.
a. two registers
b. processor register and memory stack
c. processor register and interface register
d. interface register and memory word
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14) Which control instruction is followed by an un-conditional branch instructions so as to branch to a single location from the double ones with respect to specified status-bit condition?
a. Jump instruction
b. Branch instruction
c. Skip instruction
d. Return-from-subroutine instructions
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15) Which addressing mode execute its instructions within CPU without the necessity of reference memory for operands?
a. Implied Mode
b. Immediate Mode
c. Direct Mode
d. Register Mode
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16) What kind of addressing resemble to direct- addressing mode with an exception of possessing 2- byte instruction along with specification of second byte in terms of 8 low - order bits of memory address?
a. Present- Page Addressing
b. Zero- Page Addressing
c. Relative Addressing
d. None of the above
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17) How is the effective address of base-register calculated?
a. By addition of index register contents to the partial address in instruction
b. By addition of implied register contents to the partial address in instruction
c. By addition of index register contents to the complete address in instruction
d. By addition of implied register contents to the complete address in instruction
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Answer
Explanation
Related Ques
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ANSWER: By addition of index register contents to the partial address in instruction
Explanation:
No explanation is available for this question!
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18) Which register holds the address for a stack whose value is supposed to be directed at the topmost position?
a. Stack Pointer
b. Stack Register
c. Both a & b
d. None of the above
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19) The instructions based on the stack operations are also known as 'zero address' or 'implied instructions', because _______.
a. Address gets updated automatically in stack pointer
b. Processor can refer a memory stack without specifying the address
c. Both a & b
d. None of the above
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20) What is another name of memory stack especially given for the fundamental function performed by it?
a. Last-in-first-out (LIFO)
b. First-in-last-out (FILO)
c. First-in-first-out (FIFO)
d. Last-in-last-out (LILO)
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