1) Which among the bipolar logic families is specifically adopted for high speed applications?
a. Diode Transistor Logic (DTL)
b. Transistor Transistor Logic (TTL)
c. Emitter Coupled Logic (ECL)
d. Integrated Injection Logic (I2L)
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2) Which type of unipolar logic family exhibits its usability for the applications requiring low power consumption?
a. PMOS
b. NMOS
c. CMOS
d. All of the above
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3) Which type of output current flows towards or into the output terminal in a logic circuit?
a. Sourcing current
b. Sinking current
c. Both a and b
d. None of the above
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4) Suppose that the digital IC family has a fan out of 6. It implies that the gate can supply the current to _______ of same family.
a. 6 inputs
b. 6 outputs
c. 12 nodes
d. 12 branches
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5) Which kind of logical operation is performed by the gate shown below?
a. Logical Multiplication
b. Inversion
c. Addition/ Subtraction
d. NOT EXOR
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6) What does the below stated OR Law imply, while performing OR operation of an input with '1'?
Expression of OR Law: A+ 1 = 1
a. Output will always be equal to input
b. Output will always be high
c. Output will always be low
d. Output will always be same
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7) Which De Morgan's theorem states that the complement of a sum is equal to the product of complements?
a. AB = A + B
b. A+B = A. B
c. A+B = A.B
d. AB = A + B
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8) How is the relation specified between input and output in logic circuits?
a. Switching equations
b. Truth-table
c. Logic diagram
d. All of the above
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9) In the half subtractor combinational circuit, what does 'A' represent in the subtraction operation (A - B)?
a. Minuend bit
b. Maxend bit
c. Subtrahend bit
d. Suptrahend bit
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10) Which is an incorrect rule of binary subtraction from the following?
a. 0 – 0 = 0
b. 0 – 1 = -1
c. 1 – 0 = 1
d. 0 – 1 = 1 with borrow '1'
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11) What should be the output of converter, if a common anode display segment is to be turned 'ON'?
a. '0'
b. '1'
c. Both a and b
d. None of the above
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12) Which adder plays a crucial role in eliminating the problem associated with the inter-stage carry delay?
a. Half adder
b. full adder
c. BCD adder
d. Look-ahead carry adder
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13) Which among the following is/are responsible for the occurrence of clock skew by introducing delays from different paths of clock generator to various circuits?
a. Different length of wires
b. Gates on the paths
c. Gating of clock to control the loading of registers
d. All of the above
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14) Consider the cross-coupled inverter shown below. By performing reset and set operations, if the circuit continue to remain in reset and set states respectively,then what is the bit storage capacity of cross-coupled inverter?
a. 0
b. 1
c. 2
d. 4
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15) Which is the prohibited state/ condition in S-R latch and needs to be avoided due to unpredictable nature of output?
a. S = R = 0
b. S = 0, R = 1
c. S = 1, R = 0
d. S = R = 1
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16) What would be the characteristic equation of SR latch corresponding to the K-map schematic shown below?
a. S + RQn
b. S + RQn
c. S + RQn
d. S + RQn
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17) What does the data in parallel form of representation in registers, known as?
a. Temporal Code
b. Spectral Code
c. Special Code
d. Factorial Code
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18) Which type of triggering is shown by the D flip flops in buffer registers for the temporary storage of digital words?
a. Positive level triggering
b. Negative level triggering
c. Positive edge triggering
d. Negative edge triggering
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19) Referring to the diagram, if all inputs are loaded simultaneously and output is loaded bit by bit, then what will be the mode of operation for a shift register?
a. Serial Input Serial Output (SISO)
b. Serial Input Parallel Output (SIPO)
c. Parallel Input Serial Output (PISO)
d. Parallel Input Parallel Output ( PIPO)
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20) When the mode control pin is connected to ground, Universal Shift Register acts as _______
a. Unidirectional register
b. Bidirectional register
c. Multi-directional register
d. None of the above
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21) The output of Up counters goes on increasing due to _________
a. Transmission of clock pulses
b. Reception of clock pulses
c. Both a and b
d. None of the above
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22) If the number of states in a counter are 2n, then the value of 'n' is ________
a. Less than the number of flip flops
b. Greater than the number of flip flops
c. Equal to the number of flip flops
d. Unpredictable
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23) Which sequential circuits are applicable for counting pulses?
a. Counters
b. Flip Flops
c. Registers
d. Latches
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24) Which type of triggering phenomenon is exhibited by Counters?
a. Edge
b. Level
c. Pulse
d. All of the above
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25) Where do/does the status of memory element in a synchronous sequential circuit get/s affected due to change in input?
a. At an active edge of clock
b. At passive edge of clock
c. Both a and b
d. None of the above
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26) Which type of memory elements are used in synchronous sequential circuits?
a. Clocked Flip flops
b. Unclocked Flip flops
c. Time Delay Elements
d. All of the above
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27) According to Moore circuit, the output of synchronous sequential circuit depend/s on ______ of flip flop
a. Past state
b. Present state
c. Next state
d. External inputs
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28) From the generalized schematic of Moore circuit given below, what does the combinational circuit 'C1' known as?
a. Previous state decoder
b. Present state decoder
c. Next state decoder
d. Output state decoder
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29) Which among the following are used in programming array logic (PAL) for reducing the loading on inputs?
a. Input buffers
b. Output buffers
c. OR matrix
d. AND matrix
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30) If the number of nichrome fuse links in PAL are equal to 2M xn, then what does 'n' represent in it?
a. Number of inputs
b. Number of arrays
c. Number of outputs
d. Number of product terms
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31) Which gates are used on the output side as buffers in order to provide a programmable output polarity in PAL 16 P8 devices?
a. AND
b. OR
c. EX-OR
d. NAND
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32) How many logic gates can be implemented in the circuit by complex programmable logic devices (CPLDs)?
a. 10
b. 100
c. 1000
d. 10000
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33) Which bus is used as input data bus by the control lines for a specific duration while performing write operation?
a. Uni-directional bus
b. Bi-directional bus
c. Multi- directional
d. None of the above
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34) Which operations are executed by the control line at logic '1' level?
a. Read
b. Write
c. Store
d. All of the above
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35) Which among the following is/are a/the major disadvantage/s of dynamic memory in shift registers?
a. Less power consumption
b. High packaging density
c. Necessity of additional circuitry for time to time refreshing
d. All of the above
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Answer
Explanation
Related Ques
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ANSWER: Necessity of additional circuitry for time to time refreshing
Explanation:
No explanation is available for this question!
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36) Which among the following memories utilizes the electrical voltage for erasing purposes?
a. PROM
b. EAROM
c. RAM
d. CAM
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37) The ability of HDL to describe the performance specification of a circuit is regarded as ____
a. Test case
b. System case
c. Mark bench
d. Test bench
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38) What does an entity specify in the VHDL program format?
a. List of all libraries associated with the design
b. Code properties of VHDL
c. Input/output pins of the circuit
d. The behaviour of circuit
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39) Which among the following is the correct way of declaring the standard library in VHDL?
a. std.standard_all
b. std_standard.all
c. standard_std_all
d. std.standard.all
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40) Which mode in VHDL allows to make the signal assignments to a port of mode out by preventing it from reading?
a. In
b. Out
c. Inout
d. Buffer
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