1) Which functioning element of microcontroller generate and transmit the address of instructions to memory through internal bus?
a. Instruction Decoding Unit
b. Timing and Control Unit
c. Program Counter
d. Arithmetic Logic Unit
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2) How does the microcontroller communicate with the external peripherals/memory?
a. via I/O ports
b. via register arrays
c. via memory
d. All of the above
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3) Why do the microprocessors possess very few bit manipulating instructions?
a. Because they mostly operate on bits/ word data
b. Because they mostly operate on byte/word data
c. Both a & b
d. None of the above
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Answer
Explanation
Related Ques
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ANSWER: Because they mostly operate on byte/word data
Explanation:
No explanation is available for this question!
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4) Which minimum mode signal is used for demultiplexing the data and address lines with the assistance of an external latch in a microprocessor while accessing memory segment?
a. INTA
b. DTE
c. HOLD
d. ALE
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5) Which word size is approved to be of greater importance for performing the small computational tasks along with its storage usability feature adopted by ASCII code?
a. 4-bit
b. 8-bit
c. 16-bit
d. 32-bit
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6) Which among the below stated statements does not exhibit the characteristic feature of 16-bit microcontroller?
a. Large program & data memory spaces
b. High speed
c. I/O Flexibility
d. Limited Control Applications
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7) Which microcontrollers offer the provisional and salient software features of fault handling capability, interrupt vector efficiency and versatile addressing?
a. TMS 1000 (4 bit)
b. TMS 7500 (8 bit)
c. Intel 8096 (16 bit)
d. Intel 80960 (32 bit)
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8) Which category of microcontrollers acquire the complete hardware configuration on its chip so as to run the particular application?
a. Embedded Memory Microcontrollers
b. External Memory Microcontrollers
c. Both a & b
d. None of the above
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9) External Memory Microcontrollers can overcome the limitations of insufficient in-built program and data memory by allowing the connections of external memory using _________
a. Serial Port Pins as address and data lines
b. Parallel Port Pins as address and data lines
c. Parallel Port Pins as address and control lines
d. Serial Port Pins as address and control lines
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10) How are the address and data buses removed in external memory type of microcontrollers?
a. Through demultiplexing by external latch & ALE signal
b. Through demultiplexing by external latch & DLE signal
c. Through multiplexing by external latch & DLE signal
d. Through multiplexing by external latch & ALE signal
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Answer
Explanation
Related Ques
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ANSWER: Through multiplexing by external latch & ALE signal
Explanation:
No explanation is available for this question!
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11) What are the significant designing issues/factors taken into consideration for RISC Processors?
a. Simplicity in Instruction Set
b. Pipeline Instruction Optimization
c. Register Usage Optimization
d. All of the above
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12) What does the compact and uniform nature of instructions in RISC processors facilitate to?
a. Compiler optimization
b. Pipelining
c. Large memory footprints
d. None of the above
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13) Which register of current procedure resemble physically similar to the parameter register of called procedure during register to register operation in an overlapping window of RISC Processors?
a. Local Register
b. Temporary Register
c. Parameter Register
d. All of the above
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14) Which architectural scheme has a provision of two sets for address & data buses between CPU and memory?
a. Harvard architecture
b. Von-Neumann architecture
c. Princeton architecture
d. All of the above
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15) Which factors/parameters contribute to an effective utilization or adoption of Harvard architecture by most of the DSPs for streaming data?
a. Greater memory bandwidth
b. Predictable nature of bandwidth
c. Both a & b
d. None of the above
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16) Which kind of multiplexing scheme is adopted by Von-Newman architecture especially for program and data fetching purposes?
a. Time Division Multiplexing
b. Frequency Division Multiplexing
c. Statistical Time Division Multiplexing
d. Code Division Multiplexing
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17) Which feature deals with the fetching of next instruction during the execution of current instruction irrespective of the memory access?
a. Fetching
b. Pre-fetching
c. Fetch & Decoding
d. All of the above
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18) What are the essential tight constraint/s related to the design metrics of an embedded system?
a. Ability to fit on a single chip
b. Low power consumption
c. Fast data processing for real-time operations
d. All of the above
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19) Which abstraction level undergo the compilation process by converting a sequential program into finite-state machine and register transfers while designing an embedded system?
a. System
b. Behaviour
c. RT
d. Logic
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20) Which characteristics of an embedded system exhibit the responsiveness to the assortments or variations in system's environment by computing specific results for real-time applications without any kind of postponement?
a. Single-functioned Characteristics
b. Tightly-constraint Characteristics
c. Reactive & Real time Characteristics
d. All of the above
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21) Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices of RS232?
a. CD & IR
b. DSR & DTR
c. RTS & CTS
d. None of the above
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22) Which among the below stated lines represent the handshaking variant usually and only controlled by the software in the handshaking process?
a. XON/ XOFF
b. DCD & GND
c. TxD & RxD
d. All of the above
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23) Match the following registers with their functions :
a. Line Status Register -------------------- 1. Set Up the communication parameters
b. Line Control Register ------------------ 2. Sharing of similar addresses
c. Transmit & Receive Buffers --------- 3. Status Determination of Tx & Rr
a. A-2, B-1, C-3
b. A-1, B-2, C-3
c. A-3, B-1, C-2
d. A-3, B-2, C-1
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24) Which protocol standard of serial communication specify the bi-directional and half-duplex form of data transmission by allowing various numbers of drivers and receivers in bus configuration?
a. RS232
b. RS2485
c. RS422
d. RS423
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25) What is the maximum device handling capacity of serial standard protocol RS485 in terms of drivers and receivers on a single line?
a. 8
b. 10
c. 16
d. 32
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26) Which mechanism automates the enabling of RS485 transceiver with an elimination of hardware handshake line during each time of the data transmission?
a. RTS Control
b. Send Data Control
c. Tri-State Control
d. Bit-wise Enable Timing Control
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27) What does an IC that initiate or enable the data transfer on bus can be regarded as, in accordance to the I2c protocol specifications?
a. Bus Master
b. Bus Slaves
c. Bus Drivers
d. Bus Data Carriers
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28) What is the directional nature of two active wires SDA & SCL usually adopted in I2C Bus for carrying the information between the devices?
a. Uni-directional
b. Bi-directional
c. Multi-directional
d. None of the above
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29) Which potential mode of operation indicate the frequent sending of byte to the slave corresponding to the reception of an acknowledge signal when it becomes desirable for the master to write to the slave during data transmission in I2C bus?
a. Master in master-transmit mode & Slave in slave-receive mode
b. Slave in slave-transmit mode & Master in master-receive mode
c. Master in master-transmit mode as well as master-receive mode
d. Slave in slave-transmit mode as well as slave-receive mode
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Answer
Explanation
Related Ques
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ANSWER: Master in master-transmit mode & Slave in slave-receive mode
Explanation:
No explanation is available for this question!
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30) Which processor has the necessity of manual optimization for the generation of assembly language code especially for the embedded systems?
a. RISC
b. CISC
c. Both a & b
d. None of the above
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