1) How many clock pulses are confined by each machine cycle of Peripheral-Interface Controllers?
a. 4
b. 8
c. 12
d. 16
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2) Which flags are more likely to get affected in status registers by Arithmetic and Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution?
a. Carry (C) Flags
b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above
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3) What is the execution speed of instructions in PIC especially while operating at the maximum value of clock rate?
a. 0.1 μs
b. 0.2 μs
c. 0.4 μs
d. 0.8 μs
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4) Which operational feature of PIC allows it to reset especially when the power supply drops the voltage below 4V?
a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
d. None of the above
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5) Which among the below stated reasons is/are responsible for the selection of PIC implementation/design on the basis of Harvard architecture instead of Von-Newman architecture?
a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single instruction cycle
c. Independent bus access provision to data memory even while accessing the program memory
d. All of the above
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6) Which among the below specified major functionalities is/are associated with the programmable timers of PIC?
a. Excogitation of Inputs
b. Handling of Outputs
c. Interpretation of internal timing for program execution
d. Provision of OTP for large and small production runs
a. Only C
b. C & D
c. A, B & D
d. A, B & C
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7) Which timer/s possess an ability to prevent an endless loop hanging condition of PIC along with its own on-chip RC oscillator by contributing to its reliable operation?
a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
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8) Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)
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9) Which register/s is/are mandatory to get loaded at the beginning before loading or transferring the contents to corresponding destination registers?
a. W
b. INDF
c. PCL
d. All of the above
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10) How many RPO status bits are required for the selection of two register banks?
a. 1
b. 2
c. 8
d. 16
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11) Which among the below mentioned bits specify the reset status of register in readable format and are usually utilized in sleep mode of PIC?
a. TO
b. PD
c. Both a & b
d. None of the above
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12) The RPO status register bit has the potential to determine the effective address of______
a. Direct Addressing Mode
b. Indirect Addressing Mode
c. Immediate Addressing Mode
d. Indc. Watchdog Timer (WDT) exed Addressing Mode
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13) Which status bits exhibit carry from lower 4 bits during 8-bit addition and are especially beneficial for BCD addition?
a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
d. None of the above
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14) Which statement is precise in relation to FSR, INDF and indirect addressing mode?
a. Address byte must be written in FSR before executing INDF instruction in indirect addressing mode
b. Address byte must be written in FSR after executing INDF instruction in indirect addressing mode
c. Address byte must be written in FSR at the same time during the execution of INDF instruction in indirect addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction in indirect addressing mode
a. Only A
b. Only B
c. Only A & B
d. A & D
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15) Which among the below stated registers specify the address reachability within 7 bits of address independent of RP0 status bit register?
a. PCL
b. FSR
c. INTCON
d. All of the above
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16) Where do the contents of PCLATH get transferred in the higher location of program counter while writing in PCL (Program Counter Latch)?
a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit
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17) Which condition/s of MCLR (master clear) pin allow to reset the PIC?
a. High
b. Low
c. Moderate
d. All of the above
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18) Generation of Power-on-reset pulse can occur only after __________
a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power up mode
d. the detection of current limiting factor
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Answer
Explanation
Related Ques
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ANSWER: the detection of increment in VDD from 1.5 V to 2.1 V
Explanation:
No explanation is available for this question!
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19) What is the rate of power up delay provided by an oscillator start-up timer while operating at XT, LP and HS oscillator modes?
a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles
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20) Which kind of mode is favourable for MCLR pin for indulging in reset operations?
a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode
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21) What is the purpose of using the start-up timers in an oscillator circuit of PIC?
a. For ensuring the inception and stabilization of an oscillator in a proper manner
b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers
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Answer
Explanation
Related Ques
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ANSWER: For ensuring the inception and stabilization of an oscillator in a proper manner
Explanation:
No explanation is available for this question!
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22) Which program location is allocated to the program counter by the reset function in Power-on-Reset (POR) action modes?
a. Initial address
b. Middle address
c. Final address
d. At any address reliable for reset operations
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23) When does it become very essential to use the external RC components for the reset circuits?
a. Only if initialization is necessary for RAM locations
b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if current limiting factor increases rapidly
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Answer
Explanation
Related Ques
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ANSWER: Only if VDD power-up slope is insufficient at a requisite level
Explanation:
No explanation is available for this question!
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24) Which among the below mentioned PICs do not support the Brown-Out-Reset (BOR) feature?
a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
a. A & B
b. C & D
c. A & C
d. B & D
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25) Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely unique and distinct from other microcontrollers?
a. It can reset the PIC automatically in running condition
b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above
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Answer
Explanation
Related Ques
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ANSWER: It can reset the PIC automatically in running condition
Explanation:
No explanation is available for this question!
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26) What happens when the supply voltage falls below 4V during the power-up timer delay of 72ms in PIC?
a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again
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27) What output is generated by OSC2 pin in PIC oscillator comprising RC components for sychronizing the peripherals with PIC microcontroller?
a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1
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28) Which form of clocking mechanism is highly efficient and reliable for crystal or ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)
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29) Which significant feature/s of crystal source contribute/s to its maximum predilection and utility as compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
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30) What is the executable frequency range of High speed (HS) clocking method by using cystal/ ceramic/ resonator or any other external clock source?
a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz
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31) How many bits are required for addressing 2K & 4K program memories of PIC 16C61 respectively?
a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits
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32) What location is attributed to 'goto Mainline' instruction in the program memory of PIC 16C61?
a. 000H
b. 004H
c. 001H
d. 011H
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33) When do the special address 004H get automatically loaded into the program counter?
a. After the execution of RESET action in program counter
b. After the execution of 'goto Mainline ' instruction in the program memory
c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value
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Answer
Explanation
Related Ques
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ANSWER: At the occurrence of interrupt into the program counter
Explanation:
No explanation is available for this question!
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34) How many bits are utilized by the instruction of direct addressing mode in order to address the register files in PIC?
a. 2
b. 5
c. 7
d. 8
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35) Which registers are adopted by CPU and peripheral modules so as to control and handle the operation of device inhibited in RFS?
a. General Purpose Register
b. Special Purpose Register
c. Special Function Registers
d. All of the above
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