1) In accordance to the scaling technology, the total delay of the logic circuit depends on ______
a. The capacitor to be charged
b. The voltage through which capacitance must be charged
c. Available current
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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2) In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance?
a. Static dissipation
b. Dynamic dissipation
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Dynamic dissipation
Explanation:
No explanation is available for this question!
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3) In high noise margin (NMH), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.
a. Driven
b. Receiving
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Receiving
Explanation:
No explanation is available for this question!
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4) Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?
a. Load capacitance
b. Supply voltage
c. Gain factor of MOS
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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5) For complex gate design in CMOS, OR function needs to be implemented by _______ connection/s of MOS.
a. Series
b. Parallel
c. Both series and parallel
d. None of the above
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Answer
Explanation
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ANSWER: Parallel
Explanation:
No explanation is available for this question!
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6) In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding _____ output.
a. 1
b. 0
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: 1
Explanation:
No explanation is available for this question!
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7) In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value.
a. Highest
b. Average
c. Lowest
d. None of the above
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Answer
Explanation
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ANSWER: Average
Explanation:
No explanation is available for this question!
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8) In DIBL, which among the following is/are regarded as the source/s of leakage?
a. Subthreshold conduction
b. Gate leakage
c. Junction leakage
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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9) In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials.
a. Increases
b. Remains constant
c. Decreases
d. None of the above
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Answer
Explanation
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ANSWER: Increases
Explanation:
No explanation is available for this question!
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10) Which type of MOSFET exhibits no current at zero gate voltage?
a. Depletion MOSFET
b. Enhancement MOSFET
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Enhancement MOSFET
Explanation:
No explanation is available for this question!
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