Flip Flops - Electronic Engineering (MCQ) questions & answers

1)   Which among the following is not a mode of Flip Flop representation?

a. Characteristic Equations
b. Excitation Tables
c. Finite State Machines (FSM)
d. Variable Entered Mapping (VEM)
Answer  Explanation 

ANSWER: Variable Entered Mapping (VEM)

Explanation:
No explanation is available for this question!
2)   Which flip-flop plays a vital role by functioning as the basic building block of a ripple counter?

a. S-R flip-flop
b. J-K flip-flop
c. D flip-flop
d. T flip-flop
Answer  Explanation 

ANSWER: T flip-flop

Explanation:
No explanation is available for this question!
3)   T flip- flop finds its application  in the form of frequency division since it divides the clock frequency by ________

a. 2
b. 4
c. 2n - 1
d. 4n - 1
Answer  Explanation 

ANSWER: 2

Explanation:
No explanation is available for this question!
4)   Which among the following statements is correct for the triggering associated with bistable elements?

a. Latch is level-triggered flip-flop
b. Latch is edge-triggered flip-flop
c. Flip-flop is edge-triggered latch
d. Flip-flop is not edge sensitive
Answer  Explanation 

ANSWER: Latch is level-triggered flip-flop

Explanation:
No explanation is available for this question!
5)   In delay flip-flop, _______ after the propagation delay.

a. Input follows input
b. Input follows output
c. Output follows input
d. Output follows output
Answer  Explanation 

ANSWER: Output follows input

Explanation:
No explanation is available for this question!
6)   For the schematic shown below, if the rectangular signal is applied in the form of clock signal to edge-triggered flip-flop, then where will be the change in its output?

a. Only at rising edge
b. Only at falling edge
c. Either at rising edge or falling edge
d. Neither at rising edge nor at falling edge
Answer  Explanation 

ANSWER: Either at rising edge or falling edge

Explanation:
No explanation is available for this question!
7)   What would be the characteristic equation of SR latch corresponding to the K-map schematic shown below?

a. S + RQn
b. S + RQn
c. S + RQn
d. S + RQn
Answer  Explanation 

ANSWER: S + RQn

Explanation:
No explanation is available for this question!
8)   Which is the prohibited state/ condition in S-R latch and needs to be avoided due to unpredictable nature of output?

a. S = R = 0
b. S = 0, R = 1
c. S = 1, R = 0
d. S = R = 1
Answer  Explanation 

ANSWER: S = R = 1

Explanation:
No explanation is available for this question!
9)   Consider the cross-coupled inverter shown below. By performing reset and set operations, if the circuit continue to remain in reset and set states respectively,then what is the bit storage capacity of cross-coupled inverter?

a. 0
b. 1
c. 2
d. 4
Answer  Explanation 

ANSWER: 1

Explanation:
No explanation is available for this question!
10)   Which among the following is/are responsible for the occurrence of clock skew by introducing delays from different paths of clock generator to various circuits?

a. Different length of wires
b. Gates on the paths
c. Gating of clock to control the loading of registers
d. All of the above
Answer  Explanation 

ANSWER: All of the above

Explanation:
No explanation is available for this question!

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