1) Which level of routing resources are supposed to be the dedicated lines allowing output of each tile to connect directly to every input of eight surrounding tiles?
a. Ultra-fast local resources
b. Efficient long-line resources
c. High speed, very long-line resources
d. High performance global networks
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Answer
Explanation
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ANSWER: Ultra-fast local resources
Explanation:
No explanation is available for this question!
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2) In spartan-3 family architecture, which programmable functional element accepts two 18 bit binary numbers as inputs and computes the product?
a. Configurable Logic Blocks
b. Input Output Blocks
c. Block RAM
d. Multiplier Blocks
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Answer
Explanation
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ANSWER: Multiplier Blocks
Explanation:
No explanation is available for this question!
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3) An antifuse element initial provides ______ between two conductors in absence of the application of sufficient programming voltage.
a. Conduction
b. Insulation
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Insulation
Explanation:
No explanation is available for this question!
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4) Which type of CPLD packaging comprises pins on all four sides that wrap around the edges of chip?
a. Plastic-Leaded Chip Carrier (PLCC)
b. Quad Flat Pack (QFP)
c. Ceramic Pin Grid Array (PGA)
d. Ball Grid Array (BGA)
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Answer
Explanation
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ANSWER: Plastic-Leaded Chip Carrier (PLCC)
Explanation:
No explanation is available for this question!
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5) Simple Programmable Logic Devices (SPLDs) are also regarded as _____________.
a. Programmable Array Logic (PAL)
b. Generic Array Logic (GAL)
c. Programmable Logic Array (PLA)
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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6) Which among the following is/are not suitable for in-system programming?
a. EPROM
b. EEPROM
c. Flash
d. All of the above
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Answer
Explanation
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ANSWER: EPROM
Explanation:
No explanation is available for this question!
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7) The devices which are based on fusible link or antifuse are _________time/s programmable.
a. one
b. two
c. four
d. infinite
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Answer
Explanation
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ANSWER: one
Explanation:
No explanation is available for this question!
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8) Which programming technology/ies is/are predominantly associated with SPLDs and CPLDs?
a. EPROM
b. EEPROM
c. FLASH
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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9) In fusible link technologies, the undesired fuses are removed by the pulse application of _____voltage & current to device input.
a. Low
b. Moderate
c. High
d. All of the above
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Answer
Explanation
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ANSWER: High
Explanation:
No explanation is available for this question!
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10) An Antifuse programming technology is predominantly associated with _____.
a. SPLDs
b. FPGAs
c. CPLDs
d. All of the above
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Answer
Explanation
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ANSWER: FPGAs
Explanation:
No explanation is available for this question!
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