1) In AM detector using PLL, the phase detector is basically a multiplier which produces ________components of frequencies at its output.
a. Sum
b. Difference
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Both a and b
Explanation:
No explanation is available for this question!
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2) For a PLL IC 565 with timing resistor & timing capacitor of about 15 kΩ & 0.02μF respectively, what would be the value of output frequency (f0)?
a. 433.33 Hz
b. 833.33 Hz
c. 1000 Hz
d. 2500 Hz
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Answer
Explanation
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ANSWER: 833.33 Hz
Explanation:
No explanation is available for this question!
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3) In VCO IC 566, the value of charging & discharging is dependent on the voltage applied at ______.
a. Triangular wave output
b. Square wave output
c. Modulating input
d. All of the above
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Answer
Explanation
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ANSWER: Modulating input
Explanation:
No explanation is available for this question!
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4) According to transfer characteristics of PLL, the phase error between VCO output & incoming signal must be maintained between _______ in order to maintain a lock.
a. 0 & π
b. 0 & π/2
c. 0 & 2π
d. π & 2π
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Answer
Explanation
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ANSWER: 0 & π
Explanation:
No explanation is available for this question!
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5) Which characteristic of PLL is defined as the range of frequencies over which PLL can acquire lock with the input signal?
a. Free-running state
b. Pull-in time
c. Lock-in range
d. Capture range
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Answer
Explanation
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ANSWER: Capture range
Explanation:
No explanation is available for this question!
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6) In PLL, the capture range is always _________the lock range.
a. Greater than
b. Equal to
c. Less than
d. None of the above
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Answer
Explanation
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ANSWER: Less than
Explanation:
No explanation is available for this question!
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7) Once the phase is locked, the PLL tracks the variation in the input frequency. This indicates that _____
a. Output frequency changes by same amount as that of input frequency
b. Output frequency does not change as that of input frequency
c. There is no relation between input & output frequencies
d. None of the above
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Answer
Explanation
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ANSWER: Output frequency changes by same amount as that of input frequency
Explanation:
No explanation is available for this question!
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8) In the locked state of PLL, the phase error between the input & output is _________.
a. Maximum
b. Moderate
c. Minimum
d. All of the above
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Answer
Explanation
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ANSWER: Minimum
Explanation:
No explanation is available for this question!
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9) In communication circuits, PLL is currently applicable for __________
a. Demodulation applications
b. Tracking a carrier or synchronizing signal
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Both a and b
Explanation:
No explanation is available for this question!
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10) Basically, PLL is used to lock _______
a. Its output frequency
b. Phase to the frequency
c. Phase of the input signal
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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