1) Which among the following statement/s is/are not an/the advantage/s of Programmable Logic Devices (PLDs)?
a. Short design cycle
b. Increased space requirement
c. Increased switching speed
d. All of the above
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Answer
Explanation
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ANSWER: Increased space requirement
Explanation:
No explanation is available for this question!
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2) What do the Programmable Logic Devices (PLDs) designed specially for the combinational circuits comprise?
a. Only gates
b. Only flip flops
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Only gates
Explanation:
No explanation is available for this question!
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3) In JTAG programming, JTAG stands for ________
a. Joint Texture Analysis Group
b. Joint Technique Aided Group
c. Joint Testing Array Group
d. Joint Test Action Group
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Answer
Explanation
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ANSWER: Joint Test Action Group
Explanation:
No explanation is available for this question!
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4) What would happen, if smaller logic modules are utilized for performing logical functions associated with FPGA?
A. Propagation delay will increase
B. FPGA area will increase
C. Wastage of logic modules will not be prevented
D. Number of interconnected paths in device will decrease
a. A & B
b. C & D
c. A & D
d. B & C
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Answer
Explanation
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ANSWER: A & B
Explanation:
No explanation is available for this question!
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5) What is/are the configurable functions of each and every IOBs connected around the FPGA device from the operational point of view?
a. Input operation
b. Tristate output operation
c. Bi-directional I/O pin access
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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6) Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins?
a. PLCC
b. QFP
c. PGA
d. BGA
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Answer
Explanation
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ANSWER: BGA
Explanation:
No explanation is available for this question!
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7) How many logic gates can be implemented in the circuit by complex programmable logic devices (CPLDs)?
a. 10
b. 100
c. 1000
d. 10000
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Answer
Explanation
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ANSWER: 10000
Explanation:
No explanation is available for this question!
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8) Which gates are used on the output side as buffers in order to provide a programmable output polarity in PAL 16 P8 devices?
a. AND
b. OR
c. EX-OR
d. NAND
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Answer
Explanation
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ANSWER: EX-OR
Explanation:
No explanation is available for this question!
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9) If the number of nichrome fuse links in PAL are equal to 2M xn, then what does 'n' represent in it?
a. Number of inputs
b. Number of arrays
c. Number of outputs
d. Number of product terms
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Answer
Explanation
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ANSWER: Number of product terms
Explanation:
No explanation is available for this question!
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10) Which among the following are used in programming array logic (PAL) for reducing the loading on inputs?
a. Input buffers
b. Output buffers
c. OR matrix
d. AND matrix
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Answer
Explanation
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ANSWER: Input buffers
Explanation:
No explanation is available for this question!
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