1) What is/are the necessity/ies of Simulation Process in VHDL?
a. Requirement to test designs before implementation & usage
b. Reduction of development time
c. Decrease the time to market
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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2) Timing analysis is more efficient with synchronous systems whose maximum operating frequency is evaluated by the _________path delay between consecutive flip-flops.
a. shortest
b. average
c. longest
d. unpredictable
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Answer
Explanation
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ANSWER: longest
Explanation:
No explanation is available for this question!
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3) Which functions are performed by static timing analysis in simulation?
a. Computation of delay for each timing path
b. Logic analysis in a static manner
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Both a and b
Explanation:
No explanation is available for this question!
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4) An event is nothing but ______ target signal, which is to be updated.
a. Fixed
b. Change on
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Change on
Explanation:
No explanation is available for this question!
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5) Which concept proves to be beneficial in acquiring concurrency and order independence?
a. Alpha delay
b. Beta delay
c. Gamma delay
d. Delta delay
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Answer
Explanation
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ANSWER: Delta delay
Explanation:
No explanation is available for this question!
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6) After an initialization phase, the simulator enters the ______phase.
a. Compilation
b. Elaboration
c. Execution
d. None of the above
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Answer
Explanation
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ANSWER: Execution
Explanation:
No explanation is available for this question!
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7) Which among the following is not a characteristic of 'Event-driven Simulator'?
a. Identification of timing violations
b. Storage of state values & time information
c. Time delay calculation
d. No event scheduling
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Answer
Explanation
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ANSWER: No event scheduling
Explanation:
No explanation is available for this question!
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8) Which type of simulator/s neglect/s the intra-cycle state transitions by checking the status of target signals periodically irrespective of any events?
a. Event-driven Simulator
b. Cycle-based Simulator
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Cycle-based Simulator
Explanation:
No explanation is available for this question!
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9) In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator?
a. Compilation
b. Elaboration
c. Initialization
d. Execution
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Answer
Explanation
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ANSWER: Elaboration
Explanation:
No explanation is available for this question!
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10) Which type of simulation mode is used to check the timing performance of a design?
a. Behavioural
b. Switch-level
c. Transistor-level
d. Gate-level
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Answer
Explanation
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ANSWER: Gate-level
Explanation:
No explanation is available for this question!
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