1) Basically, an observability of an internal circuit node is a degree to which one can observe that node at the _______ of an integrated circuit.
a. Inputs
b. Outputs
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Outputs
Explanation:
No explanation is available for this question!
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2) High observability indicates that ________number of cycles are required to measure the output node value.
a. More
b. Equal
c. Less
d. None of the above
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Answer
Explanation
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ANSWER: Less
Explanation:
No explanation is available for this question!
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3) Due to the limitations of the testers, the functional test is usually performed at speed _______the target speed.
a. Lower than
b. Equal to
c. Greater than
d. None of the above
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Answer
Explanation
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ANSWER: Lower than
Explanation:
No explanation is available for this question!
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4) Which among the following is/are responsible for the occurrence of 'Delay Faults'?
a. Variations in circuit delays & clock skews
b. Improper estimation of on-chip interconnect & routing delays
c. Aging effects & opens in metal lines connecting parallel transistors
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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5) Why is multiple stuck-at fault model preferred for DUT?
a. Because single stuck-at fault model is independent of design style & technology
b. Because single stuck-at tests cover major % of multiple stuck-at faults & unmodeled physical defects
c. Because complexity of test generation is reduced to greater extent in multiple stuck-at fault models
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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6) Which type/s of stuck at fault model exhibit/s the reduced complexity level of test generation?
a. Single
b. Multiple
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Multiple
Explanation:
No explanation is available for this question!
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7) Stuck open (off) fault occur/s due to _________
a. An incomplete contact (open) of source to drain node
b. Large separation of drain or source diffusion from the gate
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Both a and b
Explanation:
No explanation is available for this question!
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8) Which among the following faults occur/s due to physical defects?
a. Process variations & abnormalities
b. Defects in silicon substrate
c. Photolithographic defects
d. All of the above
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Answer
Explanation
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ANSWER: All of the above
Explanation:
No explanation is available for this question!
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9) Which among the following is regarded as an electrical fault?
a. Excessive steady-state currents
b. Delay faults
c. Bridging faults
d. Logical stuck-at-0 or stuck-at-1
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Answer
Explanation
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ANSWER: Excessive steady-state currents
Explanation:
No explanation is available for this question!
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10) In testability, which terminology is used to represent or indicate the formal evidences of correctness?
a. Validation
b. Verification
c. Simulation
d. Integration
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Answer
Explanation
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ANSWER: Verification
Explanation:
No explanation is available for this question!
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