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Interrupts Initialization of 8051 - MCQs with Answers
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Microcontrollers & Applications - 8051 Architecture
-06/12/15
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Interrupts Initialization of 8051 - MCQs with Answers
Q1. Match the following :
A. ISS --------------------------------------- 1. Monitors the status of interrupt pin
B. IER --------------------------------------- 2. Allows the termination of ISS
C. RETI ------------------------------------- 3. MCS-51 Interrupts Initialization
D. INTO ------------------------------------ 4. Occurrence of high to low transition level
Codes :
a. A-1, B-2, C-3, D-4
b. A-3, B-2, C-4, D-1
c. A-1, B-3, C-2, D-4
d. A-4, B-3, C-2, D-1
View Answer / Hide Answer
ANSWER: c. A-1, B-3, C-2, D-4
Q2. What kind of triggering configuration of external interrupt intimate the signal to stay low until the generation of subsequent interrupt?
a. Edge - Triggering
b. Level Triggering
c. Both a & b
d. None of the above
View Answer / Hide Answer
ANSWER: b. Level Triggering
Q3. Which among the below mentioned reasons is / are responsible for the generation of Serial Port Interrupt ?
A. Overflow of timer/counter 1
B. High to low transition on pin
INT1
C. High to low transition on pin
INT0
D. Setting of either TI or RI flag
Codes :
a. A & B
b. Only B
c. C& D
d. Only D
View Answer / Hide Answer
ANSWER: d. Only D
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