Timer 0 & Watchdog Timer in PIC 16C61/71 Timers - MCQs with answers

Timer 0 & Watchdog Timer in PIC 16C61/71 Timers - MCQs with answers


1. How much delay is required to synchronize the external clock at TOCKI in Timer '0' of PIC 16C61?

a. 2- cycles
b. 4- cycles
c. 6-cycles
d. 8-cycles

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ANSWER: a. 2- cycles



2. Which command enables the PIC to enter into the power down mode during the operation of watchdog timer(WDT)?

a. SLEEP
b. RESET
c. STATUS
d. CLR

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ANSWER: a. SLEEP



3. Which bits play a crucial role in specifying the details or reasons associated with the system wake-up in WDT?


a.PD & TO
b. C & Z
c. DC & RPO
d. All of the above

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ANSWER: PD & TO


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