1) What does the group of bits possessing certain level of significance called as?
a. Code
b. Bite
c. Word
d. All of the above
|
2) Which gate configuration permits the application of different independent sources at a given single node?
a. OR gate
b. Non-linear mixing gate
c. Both a & b
d. None of the above
|
3) An OR-gate configuration has an ability to reduce the interaction of the sources on one another & precisely renowned as _______.
a. Buffer circuit
b. Non-linear mixing circuit
c. Coincidence circuit
d. All of the above
|
4) What is the conditional relationship between magnitude of output and input pulse according to the intellection of dynamic logic system irrespective of the positive and negative logic?
a. Output pulse magnitude > largest input pulse
b. Output pulse magnitude < largest input pulse
c. Output pulse magnitude = largest input pulse
d. Output pulse magnitude = smallest input pulse
|
5) The highest probable output of an AND gate is acknowledged to be 1 ________.
a. if all inputs are at 1 logic state
b. if all inputs are at 0 logic state
c. if only one input is at 1 logic state
d. Cannot predict
|
6) What is the output of an inverter with respect to less positive input?
a. less negative
b. less positive
c. more positive
d. more negative
|
7) Which component in an inverter circuit plays a crucial role in the removal of minority charge carriers at base specifically due to sudden variation of signal between logic states?
a. Load Resistor
b. Base Inductor
c. Capacitor
d. None of the above
|
8) Which of the below stated application/s employ Ex-OR gate from the arithmetic functioning point of view?
a. Matching Circuit
b. Equality Detector
c. Inequality Comparator
d. All of the above
|
9) Which gates are sequentially cascaded or involved in an entire logic-array of AND-OR-INVERT (AOI) configuration?
a. AND-OR-AND
b. AND-OR-NOT
c. AND-OR-NOR
d. AND-OR-EX-OR
|
10) Which boolean expression satisfies the logic statement condition “If A=1 & B=0 or if B=1 & A=0, then output Y =1”?
a. Y = AB + BA
b. Y = AB + BA
c. Y = A B + B A
d. Y = AB+BA
|
11) Which gate generates no output when two of its inputs are at the opposite logic level?
a. X-NOR
b. X-OR
c. XOR
d. NOR
|
12) Which gate behaves as an inversion or complementation reminder before the AND operation of inputs ?
a. OR gate
b. NOR gate
c. Bubbled AND gate
d. None of the above
|
13) Being a universal gate, it is possible for NOR gate to get converted into AND gate by inverting the inputs ______.
a. before getting applied to NOR gate
b. after getting applied to NOR gate
c. before getting applied to AND gate
d. before getting applied to AND gate
|
14) NAND & NOR are considered to be Universal gates because they are capable of performing the logical functionalities concerned to _______.
a. AND gate
b. OR gate
c. NOT gate
d. All of the above
|
15) Which among the below stated boolean expressions do not obey De-Morgan's theorem ?
a. X+Y = X . Y
b. X.Y = X + Y
c. X.Y = X+Y
d. None of the above
|
16) Which statement/s is/are considered to be precise regarding the operational behaviour of MOS transistor?
a. P-channel MOS conducts with negative gate-to-source voltage
b. N-channel MOS conducts with positive gate-to-source voltage
c. Either type of device gets turned with zero gate-to-source voltage
d. All of the above
|
17) What is the effect on the power supply voltage due to substantial reduction in the duration of propagation delay and noise margin of CMOS circuit?
a. Power supply voltage increases
b. Power supply voltage decreases
c. Power supply voltage remains stable
d. None of the above
|
18) How is the configuration strategy of p-type and n-type units in two-input CMOS NAND gate circuit ?
a. Two p-type units in series & two n-type units in parallel
b. Two p-type units in parallel & two n-type units in series
c. Both p-type & n-type units in parallel
d. Both p-type & n-type units in series
|
Answer
Explanation
Related Ques
|
ANSWER: Two p-type units in parallel & two n-type units in series
Explanation:
No explanation is available for this question!
|
|
19) What is the output level of two-input CMOS NOR gate circuit configuration when all inputs are at low logic level ?
a. High
b. Low
c. Moderate
d. Cannot predict
|
20) Which law of boolean algebra emphasizes the elimination of brackets from logical expression along with the re-arrangement of grouping variables?
a. Distributive Law
b. Commutative Law
c. Associative Law
d. None of the above
|
