1) Register transfer level description specifies all of the registers in a design & ______ logic between them.
a. Sequential
b. Combinational
c. Both a and b
d. None of the above
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Answer
Explanation
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ANSWER: Combinational
Explanation:
No explanation is available for this question!
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2) If a port is declared as buffer, then which problem is generated in hierarchical design due to mapping with port of buffer mode of other entities only?
a. Structural Modeling
b. Functional Modeling
c. Behavioral Modeling
d. Data Flow Modeling
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Answer
Explanation
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ANSWER: Structural Modeling
Explanation:
No explanation is available for this question!
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3) Why is the use of mode buffer prohibited in the design process of synthesizer?
a. To avoid mixing of clock edges
b. To prevent the occurrence of glitches & metastability
c. Because critical path has preference in placement
d. Because Maximum ASIC vendors fail to support mode buffer in libraries
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Answer
Explanation
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ANSWER: Because Maximum ASIC vendors fail to support mode buffer in libraries
Explanation:
No explanation is available for this question!
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4) If the level of fan-out is beyond a limit in synthesis, it results in an insertion of buffer by ultimate effect of _____ the speed.
a. Enhancing
b. Reducing
c. Stabilizing
d. None of the above
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Answer
Explanation
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ANSWER: Reducing
Explanation:
No explanation is available for this question!
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5) In synthesis flow, the flattening process generates a flat signal representation of _____levels.
A. AND
B. OR
C. NOT
D. EX-OR
a. A & B
b. C & D
c. A & C
d. B & D
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Answer
Explanation
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ANSWER: A & B
Explanation:
No explanation is available for this question!
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6) In synthesis flow, which stage/s is/are responsible for converting an unoptimized boolean description to PLA format?
a. Translation
b. Optimization
c. Flattening
d. All of the above
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Answer
Explanation
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ANSWER: Flattening
Explanation:
No explanation is available for this question!
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7) Which among the following is/are regarded as the function/s of translation step in synthesis process?
a. Conversion of RTL description to boolean unoptimized description
b. Conversion of an unoptimized to optimized boolean description
c. Conversion of unoptimized boolean description to PLA format
d. All of the above
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Answer
Explanation
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ANSWER: Conversion of RTL description to boolean unoptimized description
Explanation:
No explanation is available for this question!
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8) Which attribute in synthesis process specify/ies the resistance by controlling the quantity of current it can source?
a. Load attribute
b. Drive attribute
c. Arrival time attribute
d. All of the above
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Answer
Explanation
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ANSWER: Drive attribute
Explanation:
No explanation is available for this question!
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9) In synthesis process, the load attribute specify/ies the existing amount of _________load on a particular output signal.
a. Inductive
b. Resistive
c. Capacitive
d. All of the above
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Answer
Explanation
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ANSWER: Capacitive
Explanation:
No explanation is available for this question!
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10) Which among the following is an output generated by synthesis process?
a. Attributes & Library
b. RTL VHDL description
c. Circuit constraints
d. Gate-level net list
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Answer
Explanation
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ANSWER: Gate-level net list
Explanation:
No explanation is available for this question!
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